Alain Fischer @afilambda
Joined May 2014-
Tweets155
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Following361
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Building a #SOC in an #FPGA in less than (literally) 5 minutes? it is possible with #litex from @enjoy_digital . In my last post I show you how you can start with this framework and the @DigilentInc #Arty board! Check it out! controlpaths.com/2022/01/17/bui…
OK, so you can design your own #riscv in VERILOG, it is nice, but what can you do with it beyond blinky and hello world ? Using LiteX + some simple software libraries, you can do much ! New tutorials here: github.com/BrunoLevy/lear…
In the future, it will be possible to design your own #riscv processor and run Doom on it ! You don't believe me ? And what if I tell you that the future is today ? Sources here: github.com/BrunoLevy/lear… Here running with #femtorv on @enjoy_digital's LiteX VexRiscV supported too.
In the future, it will be possible to design your own #riscv processor and run Doom on it ! You don't believe me ? And what if I tell you that the future is today ? Sources here: github.com/BrunoLevy/lear… Here running with #femtorv on @enjoy_digital's LiteX VexRiscV supported too.
NgspiceSimServer is running on windows!! Still some issues to work out but hey! End goal is to be able to ship Mosaic+SimServer+JupyterLab-desktop github.com/jupyterlab/jup…
Life is to short to use dated cli tools that suck Try these instead 🧵
With my C-to-Hardware translator and this source, you can glow a LED with a FPGA If normally compiled as software, it simulates the hardware faster than realtime: ~220MHz (uses @enjoy_digital's LiteX, @sylefeb Silice HDL as intermediate step, and was inspired on @pipelinec_hdl)
starting in 1999, ESA ran an 8 year long endurance test of Sony 18650HC Li-Ion cells. no cell balancing, charging to 4.2 V, discharging to ~30% capacity 75000 (not a typo) cycles later, no cell failures, and cells down only to ~60% of starting capacity web.archive.org/web/2016122809…
.@WerWolv's ImHex got a lot fancier since last time I tried it... github.com/WerWolv/ImHex
Yesterday I was introduced to a new education-focused @risc_v simulator, qtrvsim. It lets you visualise what is happening in single stage and pipelined CPUs running RISC-V code. And there is also a webassembly port, so it runs in the browser! dev.jakubdupak.com/qtrvsim/
I just learned that there's a terminal version of Wireshark called termshark?!?!?! this is incredible termshark.io
excamera.com/files/j1.pdf Time for my annual reading of the J1 Forth CPU paper. It's just so pretty! The way the core, the architecture and the language tile together. I still haven't clocked how he bootstrapped the toolchain so quickly, starting to see why Forth is a cult classic
why are chips often so expensive? how do chip companies determine the prices of their chips? a thread... 🧵
Saudi solar plant locks in new record low price for power: 1.04/kWh (USD cents) Costs down 21% since 2020 Portugal solar world record of 1.316/kWh ... and 82% since 2015 (5.85/kWh in Dubai) Expensive, polluting fossil fuel power is so 20th century reneweconomy.com.au/saudi-solar-pl…
❓When was the last time you printed a document? Why are we still using tools designed for printing when we don't do that anymore? It's time we re-think the humble word processor. #ship30for30 👇👇👇
Thanks to @SayehBasel it's now possible to run Linux-on-LiteX-VexRiscv on the low cost 20$ QMTECH EP4CE15, which makes it the current cheapest supported board... any PR that would reduce again the entry price is welcome :)
Successfully Ethernet enabled my @Raspberry_Pi Pico with a $2 RMII Ethernet PHY module! The RP2040’s PIO, DMA and dual-core capabilities allowed me to create the Ethernet MAC controller in software 🚀 github.com/sandeepmistry/…

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