I did some more hacking to produce a totally floorplanned 64-input sorter circuit on a Xilinx XC7A200T FPGA, on the LHS picture shown as a tight rectangular block, on the RHS a close-up that shows the butterfly wiring pattern. Produced from a hardware DSL written in Haskell using…
I wrote my first and maybe only Substack post. This is a follow up to my Colwell post where I found a 2007 technical report by two Microsoft employees who interviewed folks from MS, AMD and Intel about the history of the transition, and I learned a lot!
computerparkitecture.substack.com/p/the-long-mod…
I wrote my first and maybe only Substack post. This is a follow up to my Colwell post where I found a 2007 technical report by two Microsoft employees who interviewed folks from MS, AMD and Intel about the history of the transition, and I learned a lot!
computerparkitecture.substack.com/p/the-long-mod… https://t.co/djpPRqEoAC
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