Carbon @emsysfpga

Embedded systems enthusiast. Joined July 2021

Tweets

581
Followers

43
Following

351
Likes

3K

PlatformIO @PlatformIO_Org

a week ago

Microsoft leverages PlatformIO for its course "IoT for Beginners" 🎓 A free, open-source, 12-week/24-lesson #IoT curriculum designed for beginners by the @azureadvocates 👉 piolabs.com/blog/news/micr… 📌 #OpenSource #EmbeddedSystems #Semiconductor #Engineering #Electronics #IDE #CLI

0 7 24 1K 16

Download Image

There is a lot to like about the newly released ngscopeclient. Some of my favorite features: • Broad hardware support including open source devices • Wide array of complex protocol analysis options • Runs on Linux, Windows and Mac OS • Freely available and open-source If…

3 18 101 6K 58

Download Image

Carbon @emsysfpga

3 months ago

Working with a couple of MCU HALs I've always promoted an unsigned long macro to a pointer myself. Passing an address as unsigned long and see it's pointer promotion silenced inside their API though reasonable, is still hurtful to me. #VitisSDK

0 0 0 34 0

Download Image

Carbon @emsysfpga

3 months ago

Maybe it's just me. Vivado+ Vitis Unified IDE on Ubuntu is such a pain.

1 0 1 80 0

Carbon @emsysfpga

3 months ago

Does anyone do RTL to overcome loneliness?

0 0 6 154 0

Kevin Hubbard @bml_khubbard

3 months ago

I’ve completed my year-long journey to becoming a published author in electrical engineering. Mastering FPGA Chip Design: For Speed, Area, Power, and Reliability is now part of the Elektor Academy Pro series and available in both print and eBook formats: elektor.com/products/maste…

12 26 271 17K 170

Adam Taylor @ATaylorFPGA

4 months ago

I get asked a lot how to get started with FPGAs, so this week we are going to right back to the beginning and take a look at how to get started with the ZUBoard and Vivado 2025.1 adiuvoengineering.com/post/microzed-…

1 19 177 8K 118

Download Image

Carbon @emsysfpga

9 months ago

Took this whole weekend to write i2c controller RTL for MCP4725 DAC. Claude reviewed the design, found bugs and gave plethora of improvement points. In the end generated state machine diagram as well. Though the design is bare minimal, I learnt a lot. Such a bliss to write RTL.