Moe L @lioumo

Real life, baby

大家以為 NVIDIA 只是要把交換器的光模組換成 CPO，其實真正要換光的是 GPU 跟 GPU 之間的 NVLink。 NVIDIA 跟思科一起推插拔式的 USFP，單通道 400G，一個模組 6.4T。那條線是櫃跟櫃之間的網路，插拔式不會死。 這次 Ian Buck 在 OCP 講的是另一條線：現在一櫃 72 顆 GPU 連成一台，他說明年要做到 576 顆，理由是 10 兆參數的模型一櫃已經裝不下。 72 到 576 是 8 倍。銅線就像延長線，房間裡很好用，拉到隔壁棟就不行了。 所以會有兩條光：對外的網路走插拔式，對內的 NVLink 走 CPO。雷射跟光纖對準的需求是兩邊加起來，不是一邊取代另一邊。 數字是 NVIDIA 喊的，雷射是 Lumentum 要生出來的。

Leonard @Leoskie_L

2 weeks ago

CPO 一來，光模組就死了。 這週 OCP 上，推 CPO 最兇的輝達，反而和思科一起發表了一個新的插拔式光模組規格：USFP。 規格是每通道 400G。第一代 16 通道，放在和現在 OSFP 差不多大的空間裡；思科部落格寫明，16 通道是 6.4T，未來擴到 32 通道是 12.8T。 網路上「6.4T 還是

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That’s why we had to cut RAM in half for Optimus lol.😂

Elon Musk @elonmusk

3 weeks ago

@Bqlsj2023 “This is why RAM is so expensive” 🤣🤣

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英伟达上周又历史新高了 我看B站除了好多恶搞视频 不得不说，现在Ai做视频，基本看不出来痕迹 太夸张了

Someone used Claude Opus 5.5 to make a 3D animation of Nvidia Blackwell GPUs (from server down to an atom). Took 1 hour and full animation “runs from single HTML file, directly in browser. No vid editor. No pre-rendered 3D sequence. Just browser-based experience.” Very cool.

Starship Flight 14, the first morning launch from Starbase since Flight 5

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This is how we survive

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SpaceX @SpaceX

4 weeks ago

Liftoff of Starship's first orbital flight

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Liftoff of Starship's first orbital flight

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TSMC to Stick With Microbumps Over Hybrid Bonding for HBM Packaging for Now, Tasks Suppliers With 5μm Development Taiwan’s TSMC is expected to continue using conventional microbump technology, rather than hybrid bonding, for advanced packaging that connects high-bandwidth memory (HBM) with AI accelerators for the time being. Given the development cycle for related materials, finer-pitch microbumps are expected to remain in use through the later stages of HBM4 and into the early phase of HBM5. According to materials industry sources on September 2, TSMC has asked its materials and equipment partners to develop bonding and underfill solutions for approximately 5-micrometer (μm)-class bumps. In other words, TSMC wants the microbumps currently used in advanced packaging to become even shorter and finer. Korean and Japanese suppliers have begun development, with mass production of 5μm-class bumps estimated to begin in the second half of 2028. Currently, bump heights are approximately 15–25μm for third-generation extended HBM, or HBM3E, while HBM4 is approaching roughly 10μm. Japanese materials suppliers have previously said they have difficulty guaranteeing quality below 15μm. A 5μm bump would therefore fall well below the current qualification threshold. The reason for making the bumps shorter and finer is the height limit of the HBM cube and the need for higher interconnect density. Under JEDEC specifications, the maximum HBM stack height is 775μm. The number of I/O connections continues to increase, but the overall stack must remain within this height limit. In TSMC’s advanced CoWoS packaging, the GPU and the HBM stack—already assembled by the memory supplier—are mounted onto a silicon interposer using microbumps. The stacking of 16 DRAM dies itself is performed within the HBM package by companies such as SK hynix and Samsung Electronics, rather than by TSMC. However, as the number of interconnects on the accelerator side increases, the microbumps used to mount the devices in CoWoS also need to become shorter and more densely packed. First- and second-generation HBM used relatively large solder bumps. As the number of stacked dies and I/O connections increased, microbumps became the mainstream approach around the HBM3 generation. SK hynix has used its MR-MUF process, in which liquid underfill is applied after mass reflow, while Samsung Electronics has used TC-NCF, which places a film-type underfill between the dies before thermocompression bonding. Hybrid bonding has been discussed as the next step. By eliminating bumps and directly bonding copper pads, the interconnect can be made thinner and significantly denser. TSMC already uses this technology, under the SoIC platform, for stacking logic chips. However, HBM is still attached to the interposer using microbumps. The industry has been reluctant to abandon a process that is already proven in terms of yield, inspection, and high-volume manufacturing. At the 5μm scale, manufacturers must simultaneously solve issues involving void-free underfill, residual flux, and bonding alignment. Given the level of difficulty, TSMC appears to have distributed different development tasks across its materials and equipment partners. The direction within the HBM stack itself is similar. At Hot Chips 2026 last month, SK hynix indicated a roadmap under which it would continue using microbump-based MR-MUF through HBM4 and HBM4E, rather than adopting hybrid bonding. Direct bonding was positioned as a technology for HBM5 and for stacks exceeding 20 dies. Industry observers believe JEDEC’s decision to raise the maximum HBM stack height from 720μm to 775μm has provided additional headroom to extend the use of microbumps. A materials industry source said, “TSMC’s request to develop finer microbumps can be interpreted as a signal that, for this generation, it intends to use lower-profile microbumps rather than move to direct bonding.” The source added, “Microbumps below 15μm have already been developed, but guaranteeing their quality remains difficult. The key challenge is not so much the bump itself, but developing an underfill solution that can reliably support and qualify it.”

@investment90511 請問雷鳥大不看好立隆電後續嗎？

@investment90511 雷鳥大，愛您

世界第一CEO搶台灣路人的烤玉米吃 剛剛真實發生 非AI 台灣女網友發文： 在夜市遇到黃仁勳不稀奇 被湊過來問好不好吃，然後手上這隻就⋯ No 我的烤玉米～～～ 真的太有趣太興奮了

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記憶體晶片廠商在第一季財報後，對擴張HBM（高頻寬記憶體）產能的態度明顯轉趨保守。 主要原因有三： 一是傳統DRAM（尤其是LPDDR5）目前獲利遠高於HBM； 二是HBM4訂單成長力道略顯疲弱； 三是基於NAND的KV cache記憶體AI推論快速崛起，導致部分原本規劃用於HBM的資本支出，轉向投入傳統DRAM與NAND領域。 此外，晶片廠對簽訂LTA（長期合約）的意願也降低。隨著客戶願意接受每季更高的合約價格，廠商擔心若鎖定長期價格，將錯失供給短缺延續至2027-28年的獲利機會，或在景氣下滑時面臨合約風險。 整體來看，2026下半年至2027上半年，記憶體廠獲利成長將更仰賴傳統記憶體，而非HBM4。新簽LTA長期合約可能趨緩，多數銷售仍以每季議價為主。

stf @stfbutnou

6 months ago

BAC: Some chipmakers alluded to reduced interest in LTA (long-term agreement)-based chip sales, given the growing number of customers paying higher DRAM and NAND contract prices each quarter. Chipmakers’ concerns (about LTA) are limited price/profit upside If memory chip supply

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AI資料中心引爆光通訊雷射荒，NVIDIA固盤EML重塑供應鏈 TrendForce最新報告指出，AI資料中心大規模叢集化帶動800G以上光收發模組需求暴衝，2025年全球出貨達2400萬支，2026年更飆至6300萬支，年增2.6倍。 需求最上游的雷射光源已成最大瓶頸。NVIDIA為確保Blackwell平台供貨，策略性包下Lumentum、Coherent、Mitsubishi、Sumitomo等主要EML（電吸收調變雷射）廠商產能，交期已排到2027年後，導致市面EML嚴重缺貨。 EML因整合調變功能、製程難度高，全球供應商屈指可數，成為AI長距傳輸關鍵戰略物資。NVIDIA此舉雖穩固自身供應，卻逼非NVIDIA陣營CSP與模組廠加速轉向CW（連續波）雷射＋矽光子方案。 CW雷射結構簡單、進入門檻較低，廠商較多，但產能擴充受限於設備交期與後段切割、老化測試，同樣供不應求。 同時，200G高速PD（光二極體）需求同步爆發。因同樣使用InP磊晶，雷射廠優先排產雷射晶片，剩餘InP磊晶產能外溢至台廠iET、全新等專業磊晶廠，迎來顯著訂單。 NVIDIA壟斷EML策略意外加速CW＋矽光子技術落地，同時掀起整條光通訊雷射供應鏈產能爭奪戰與格局重組，具高階InP磊晶能力的台廠成為最大受惠者。

歌が上手い人を探しています！ 興味のある方、推薦があればDMください！🙇 作品が聴けるURLを添えてもらえると大変助かります🙇 よろしくお願いします🙇

中華人民共和国大使館前、媚中館長陳之漢玉音放送 中华人民共和国大使馆前、舔共馆长陈之汉玉音放送

@stockwilsonrice 終於更新了！！ 等了一個下午 手在發抖了⋯🥲🥲

@stockwilsonrice Wilson 好節目，每集必聽，愛您！

爆豪勝己に投票しました!! #WORLDBESTHERO #PlusUltraStage #TheMhaIsBakugo myheroacademia.worldbesthero.com/ja/final-vote/…

看到有大哥拋玉！ 小弟我做了一個可以自動抓trendforce 每日報價資料的Google sheet(我就懶🥵)，有興趣的自行取用！ docs.google.com/spreadsheets/d…

SBG @SBG_jerry_1006

2 years ago

DDR4起飛🛫

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