Wow, great article on working with #FPGAs. Couldn't agree more that manual by hand pipelining is annoying and tools should do it for you 🤓 #hardware #hdl #hls #eda stitt-hub.com/its-time-to-re…

@pipelinec_hdl Pipelining at HDL level is fine but generally more effective is auto pipelining at PnR stage. Vivado does support that and I really recommend that instead.