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SpinalHDL @SpinalHDL

Joined June 2015
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SpinalHDL @SpinalHDL

3 years ago

SpinalHDL webinar the 16 december : datenlord.github.io/en/spinal.html

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SpinalHDL @SpinalHDL

9 years ago

New #SpinalHDL documentation : spinalhdl.github.io/SpinalDoc Help yourself : Try it for your next #FPGA #ASIC project instead of #VHDL #Verilog

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SpinalHDL @SpinalHDL

10 years ago

@3yakuya Try spinalHDL :) It's a scala library that allow you to describe your hardware without using this rock age #VHDL !

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SpinalHDL @SpinalHDL

10 years ago

SpinalHDL is a #scala internal DSL that allow the user to remplace #vhdl and #verilog for RTL without their limitations.

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