Picture

Zip CPU @zipcpu

FPGA design engineer and blogger, placing particular emphasis on test and formal verification zipcpu.com Gisselquist Technology, LLC, Joined January 2017
  • Tweets
    7K
  • Followers
    8K
  • Following
    152
  • Likes
    3K
Zip CPU retweeted
zipcpu Profile Picture

Zip CPU @zipcpu

3 days ago

@lel0uch_vb Thank you, you are right, I grabbed the wrong section of the file. This would be where I see multiple drivers. Both STATUS and DATA appear multiply driven.

zipcpu Profile Picture

Zip CPU @zipcpu

5 days ago

What do you think ... is 1'b00 an error?

zipcpu Profile Picture

Zip CPU @zipcpu

5 days ago

Customer: If I adjust your file order, your regression simulations fail I'm simulating w/ Cadence. This is weird. If I don't delete the cache between simulation runs, the bug is masked. Hmmm ...

zipcpu Profile Picture

Zip CPU @zipcpu

a week ago

We have a winner! After 9 days and 16 hrs (232 hrs total), Boolector has beaten Z3, Yices2 *and* CVC5. Much to my surprise, Z3 had the fastest basecase solver, but Boolector remains the fastest induction solver (for this test case).

zipcpu Profile Picture

Zip CPU @zipcpu

3 weeks ago

We have a winner! After 9 days and 16 hrs (232 hrs total), Boolector has beaten Z3, Yices2 *and* CVC5. Much to my surprise, Z3 had the fastest basecase solver, but Boolector remains the fastest induction solver (for this test case). https://t.co/3IyDVQk6Kn

zipcpu Profile Picture

Zip CPU @zipcpu

2 weeks ago

When it comes to learning digital design, I would argue there's only a small palette of tools that need to be learned. These can all be learned in a semester. Getting good with them? That could take a lifetime. What do you think?

zipcpu Profile Picture

Zip CPU @zipcpu

2 weeks ago

Now, with a new UPS, the solver race is back on. Four solvers in contention on one proof. We'll see who wins.

zipcpu Profile Picture

Zip CPU @zipcpu

3 weeks ago

Now, with a new UPS, the solver race is back on. Four solvers in contention on one proof. We'll see who wins. https://t.co/HSzLYI1XpR

zipcpu Profile Picture

Zip CPU @zipcpu

2 weeks ago

I'm thinking of writing an article on how to do "digital clock division". Sure, you can create a "new" clock signal, but the trick is to avoid transitioning any logic on that new digital signal, while keeping the IP transitioning on the original system clock

zipcpu Profile Picture

Zip CPU @zipcpu

3 weeks ago

My Dad, a CrayOS developer, once tried to write a language he called "D". I'm not sure if it ever made it out of his office. It certainly never caught on.

davepl1968 Profile Picture

Dave W Plummer @davepl1968

3 weeks ago

My Dad, a CrayOS developer, once tried to write a language he called "D". I'm not sure if it ever made it out of his office. It certainly never caught on.

zipcpu Profile Picture

Zip CPU @zipcpu

3 weeks ago

Second test failed when the power browned out after 7 hrs. I'm now browsing UPS battery power on Amazon ...

zipcpu Profile Picture

Zip CPU @zipcpu

3 weeks ago

Second test failed when the power browned out after 7 hrs. I'm now browsing UPS battery power on Amazon ...

zipcpu Profile Picture

Zip CPU @zipcpu

3 weeks ago

See ... this is the problem I have with most of the commercial tools I have access to ... I have access to the tools, but not the courseware and ... I can't figure out where to start with their documentation. At least with open source tooling you can google any thing you need to…

beaversteever Profile Picture

Steever @beaversteever

3 weeks ago

See ... this is the problem I have with most of the commercial tools I have access to ... I have access to the tools, but not the courseware and ... I can't figure out where to start with their documentation. At least with open source tooling you can google any thing you need to…

zipcpu Profile Picture

Zip CPU @zipcpu

3 weeks ago

Well, the first test was a failure. Power's been going out here regularly every day in the late afternoon. When the CPU is on high power, the UPS can't keep up and everything shuts down. All I know so far is that the proof will take longer than 5hrs independent of the solver.

zipcpu Profile Picture

Zip CPU @zipcpu

3 weeks ago

Well, the first test was a failure. Power's been going out here regularly every day in the late afternoon. When the CPU is on high power, the UPS can't keep up and everything shuts down. All I know so far is that the proof will take longer than 5hrs independent of the solver.

Trends for United States

Jake Moody
10,9 B posts
Lions
88,4 B posts
Packers
58,6 B posts
Bo Nix
6.089 posts
Jets
107 B posts
Steelers
118 B posts
49ers
46,8 B posts
Browns
79,4 B posts
Callahan
4.330 posts
Falcons
54,8 B posts
Dolphins
70,5 B posts
#GoPackGo
9.620 posts
Kittle
7.250 posts
Niners
5.172 posts
#VMAs
163 B posts
Jordan Love
6.837 posts
Broncos
36,9 B posts
Giants
104 B posts
Goff
5.888 posts
Titans
41,6 B posts

You might like

Playing/Experimenting with FPGAs, trying to do something useful but also sharing the useless things done in the process :)
Enjoy Digital
@enjoy_digital
10K Followers
mostly about open source FPGA tools and chip design tools
Edmund Humenberger
@ico_TC
9K Followers
A non-profit, global organisation where hardware and software designers collaborate in the development of open source cores, related IP, tools and software.
OpenHW Foundation
@OpenHWFdn
4K Followers
RISC-V International is the non-profit home of the open standard RISC-V Instruction Set Architecture (ISA), related specifications, and stakeholder community.
RISC-V International
@risc_v
32K Followers
Sign up to our newsletter! https://t.co/IAGqTf45DB
YosysHQ
@YosysHQ
3K Followers
Antmicro is a software-driven tech company developing open and modern industrial edge and cloud AI systems.
Antmicro
@antmicro
5K Followers
Only hardware makes it possible! FPGA, RISC-V, 68K, OS, graphics, demos, permacomputing 🦣 https://t.co/hoDeBTqKT0
Flux
@WillFlux
4K Followers
AIoT opensource hardware platform
Sipeed
@SipeedIO
19K Followers
Open Source Hardware Geek
Tim 'mithro' Ansell
@mithro
6K Followers
lowRISC® is a not-for-profit engineering company that creates and maintains commercial-grade open silicon designs through its collaborative Silicon Commons
lowRISC
@lowRISC
7K Followers
Engineer and Technology Communication. On a mission to make ASICs more accessible. YosysHQ & Tiny Tapeout founder member. @mattvenn.net on blue sky
Matthew Venn
@matthewvenn
13K Followers
Software engineer and logic design hobbyist. Since 2021, Building RISC-V SoCs from scratch and hacking xv6/Linux to life, TU Berlin graduated
logic destroyer
@splinedrive
18K Followers
As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute. With SiFive, RISC-V has no limits!
SiFive
@SiFive
14K Followers
A joint effort of @ETH_en, University of Bologna @Unibo + partners for Parallel Ultra-Low Power computing. Boldly designing open hardware since '13.
PULP Platform
@pulp_platform
7K Followers
#kilocore #RISCV #DarkRISCV #68K #VLIW #DSP #FPGA #Verilog #C #AWK #ASM #VHDL #HPC #GPU #memes #cyberpunk #jokes
Marcelo Samsoniuk
@samsoniuk
3K Followers