Matthew Venn @matthewvenn
Engineer and Technology Communication. On a mission to make ASICs more accessible. YosysHQ & TinyTapeout founder member. @[email protected] ZeroToASICcourse.com Valencia, Spain Joined January 2009-
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This project has been something of a white whale for me. Think I've been working on it 5-6 months now? Still a lot of work to be done, but I'm finally confident in the results to share some details! I made photosensitive pixels from Copper Oxide 😎 youtube.com/watch?v=O7xH9Z…
My team and I had fun learning and doing this. Though by no means I consider myself a chip designer, taping out the design, peeking in the GDS and poking in the hardware really helps understand chips at very low levels. And gives an appreciation for the pro chip designers.
My team and I had fun learning and doing this. Though by no means I consider myself a chip designer, taping out the design, peeking in the GDS and poking in the hardware really helps understand chips at very low levels. And gives an appreciation for the pro chip designers.
Riscure's @jzvw designed a chip and taped out on Sky130, then decapped it and sniffed the AES keys with a near field probe! We talk about it in the next Efabless webinar: efabless.zoom.us/webinar/regist…
May news update for #opensource #silicon enthusiasts! Covering #TinyTapeout, events, my new #ASIC analog course, and interviews! youtube.com/watch?v=CDUOHS…
It's out! A fly over, through the lens of my #ASIC projects (including mixed-signal now!) in and #PCB work for @tinytapeout: a talk I gave at the recent @FossiFoundation @LatchUpConf in Boston. Get a preview of the #analog design, the demoboards, more youtube.com/watch?v=h4cPi4…
TT06 closed with some amazing projects on board. See this thread for details: x.com/tinytapeout/st…
TT06 closed with some amazing projects on board. See this thread for details: x.com/tinytapeout/st…
CMOS is the #ASIC terminology of the week! zerotoasiccourse.com/terminology/cm… In the last month, CMOS has been the 32nd most popular out of 42 terms.
The Z80 Is Dead. Long Live The Free Z80! hackaday.com/2024/04/28/the…
Left: the open-source Z80 core on 130 nm process inside a multi-project @tinytapeout chip. Goes into fabrication in June. Right: the original Z80 from 1976 on 4 um (4000 nm) process. Matching scale.
@luigifcruz's awesome Cyberether & FM demodulation demo running smoothly with our LiteX/LitePCIe based XTRX gateware! Thanks to @GwenhaelG hard work to reuse @MyriadRF’s LimeSuiteNG lms7002m library for our SoapySDR driver. The best of both worlds!
@Dcednz @efabless @matthewvenn Made it visual. Scales are matching.
Amazing result for TT06! And TT07 is already open - get involved!
Amazing result for TT06! And TT07 is already open - get involved!
It’s the lasted edition - hot off the press! makernews.substack.com/p/april-2024-m… #makernews
Last day to get your hands on the Raise 2 at the best price EVER!
Last hour to lock in a great price on the @DygmaLab raise 2 split keyboard! I have the original and it's the best keyboard I ever made! dygma.com/pages/dygma-ra…
I threw a quick test for Z80 tapeout using existing open-source core TV80: 1) CMOS 130nm via #TinyTapeout 07 / @efabless #ChipIgnite 2) ~4K logic gates 3) fits in 0.064 mm^2 ~ roughly 4 TT tiles 4) according to sim should run at 48 MHz Check it out: github.com/rejunity/z80-o…
I threw a quick test for Z80 tapeout using existing open-source core TV80: 1) CMOS 130nm via #TinyTapeout 07 / @efabless #ChipIgnite 2) ~4K logic gates 3) fits in 0.064 mm^2 ~ roughly 4 TT tiles 4) according to sim should run at 48 MHz Check it out: github.com/rejunity/z80-o… https://t.co/5SusvRPdLz
Step 6 ✅: Converting my design into a full chip layout With my complete Verilog design, the last step was to pass my design through the EDA flow to create a finalized chip layout. I targeted the Skywater 130nm process node for my design (which I made a few designs for 2 weeks…
I've spent the past ~2 weeks building a GPU from scratch with no prior experience. It was way harder than I expected. Progress tracker in thread (coolest stuff at the end)👇
Allow me to introduce my latest product from #logicDestroyer. A RISC-V RV32E called KianV RV32E Baremetal Edition, which consumes relatively few resources. It's equipped with an audio device, as you know from my videos, a generic SPI controller for OLED and other fun, a UART, and…
We were reviewed by @HackSpaceMag and got 10/10! "Learn how microchips work by designing one." Thanks to @efabless and all our supporters for making this possible! Read the full review here: hackspace.raspberrypi.com/issues/77
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So Norway banned smartphones in schools and 3 years later, girls’ GPAs are up, their visits to mental health professionals are down 60% and bullying in both boys and girls is down 43-46%. That’s wild
This project has been something of a white whale for me. Think I've been working on it 5-6 months now? Still a lot of work to be done, but I'm finally confident in the results to share some details! I made photosensitive pixels from Copper Oxide 😎 youtube.com/watch?v=O7xH9Z…
My team and I had fun learning and doing this. Though by no means I consider myself a chip designer, taping out the design, peeking in the GDS and poking in the hardware really helps understand chips at very low levels. And gives an appreciation for the pro chip designers.
Riscure's @jzvw designed a chip and taped out on Sky130, then decapped it and sniffed the AES keys with a near field probe! We talk about it in the next Efabless webinar: efabless.zoom.us/webinar/regist…
It's out! A fly over, through the lens of my #ASIC projects (including mixed-signal now!) in and #PCB work for @tinytapeout: a talk I gave at the recent @FossiFoundation @LatchUpConf in Boston. Get a preview of the #analog design, the demoboards, more youtube.com/watch?v=h4cPi4…
Forty-odd years ago, almost 40% of the world lived in extreme poverty. Today it's around 10%. ourworldindata.org/extreme-povert…
Forty-odd years after neoliberalism took hold it’s clear it doesn’t work. In fact, it never had either a robust theory or the data to back up its claims. Time to introduce a new, more freeing capitalism that allows all people to live up to their potential. That’s what I do in my…
this! also, there's no scientific evidence backing the claim "AI learns like humans" when we don't know how humans learn in the first place
Everyone who keeps saying "AI learns just like humans", as a sort of counter-argument to artists, realize that the "AI" is controlled, operated and profited from, by another entity, right? It's not the "AI" going out and doing art shows to pay rent. You get that, yeah?
The Z80 Is Dead. Long Live The Free Z80! hackaday.com/2024/04/28/the…
Left: the open-source Z80 core on 130 nm process inside a multi-project @tinytapeout chip. Goes into fabrication in June. Right: the original Z80 from 1976 on 4 um (4000 nm) process. Matching scale.
@luigifcruz's awesome Cyberether & FM demodulation demo running smoothly with our LiteX/LitePCIe based XTRX gateware! Thanks to @GwenhaelG hard work to reuse @MyriadRF’s LimeSuiteNG lms7002m library for our SoapySDR driver. The best of both worlds!
@splinedrive @hackaday For those of us of a certain age, the Z80 (and 6502) was the difference between owning 0 computers and 1 computer.
@Dcednz @efabless @matthewvenn Made it visual. Scales are matching.
@matthewvenn @Hal_clockwork @hackaday I have and love the devterm but this form factor is even more useful..
@Dcednz @efabless @matthewvenn It is a very good question! The original process had roughly 30 times larger features - 4000 nm vs 130 nm. So scaled down by 30 it should’ve been 120x110um. We have some room for improvement! ;)
@matthewvenn That's a great idea! The 30 min are students doing a hands-on exercise? How long are the new material lectures?
@erikvanzijst Sorry, you are right. I think this project with 16 tiles and uLinux RISC-V SoC is more #TinyTapeout. x.com/splinedrive/st…
My RISC-V uLinux ASIC SoC is 2.6 times larger than the bare metal variant, but it is an RV32IMA processor with UART, generic SPI, and a memory controller for PSRAM/flash memory to run uLinux. #tinytapeout
#TinyTapeout 6 stats! 9 meters of wire and 267000 standard cells across all projects The highest utilisation of all designs was 93% The biggest project a NIST random number generator test with 19265 cells Picture shows logic cell usage, analog designs appear mostly empty.
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