airhdl @airhdl

Create AXI4 register maps for your FPGA or ASIC project in the browser and download the generated code. airhdl.com Germany Joined December 2014

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Guy Eschemann @geschema

2 years ago

We're delighted to provide the McMaster Interdisciplinary Satellite Team (MIST) at McMaster University in Canada with free airhdl.com subscriptions to support the development of their nanosatellites! mcmasterneudose.ca mcmasterneudose.ca/supporters

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airhdl @airhdl

3 years ago

New blog: Using airhdl to Design a PN Sequence Checker for an Analog Devices ADCs airhdl.com/blog/2023/02/2…

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airhdl @airhdl

3 years ago

@airhdl has a number of beta features, which are currently being tested by a subset of our users. The full list is here: airhdl.com/docs/beta Feel free to request access in case they're of interest to you!

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airhdl @airhdl

3 years ago

Based on initial user feedback, the LFSR feedback type (XOR or XNOR) is now configuable in the user interface.

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airhdl @airhdl

3 years ago

New Generator: Linear-Feedback Shift Registers airhdl.com/blog/2022/09/1…

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airhdl @airhdl

3 years ago

You can now transfer ownership of a register map to another airhdl user. Read more about it here: airhdl.com/blog/2022/08/2…

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airhdl @airhdl

3 years ago

New blog post: How to Import 100 Registers from a Text File to airhdl airhdl.com/blog/2022/07/0…

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airhdl @airhdl

3 years ago

Shiny and New: the SPI to AXI4-Lite Bridge airhdl.com/blog/2022/06/2… #FPGA #AXI4 #VHDL #SystemVerilog

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airhdl @airhdl

3 years ago

Researchers from UC Santa Barbara using airhdl in a massively parallel probabilistic computing engine. nature.com/articles/s4192…

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airhdl @airhdl

3 years ago

KU Leuven teacher Levi Mariën uses @airhdl to teach SoC design to his master's students. airhdl.com/blog/2022/04/2… #FPGA #AXI4 #VHDL #SystemVerilog

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airhdl @airhdl

3 years ago

How to initialize 30,000 coefficients over AXI4 using airhdl (and a bit of custom logic) airhdl.com/blog/2022/04/2… #FPGA #AXI4 #VHDL #SystemVerilog

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airhdl @airhdl

4 years ago

New @airhdl feature: auto-compute register offsets #fpga #axi4 #vhdl #systemverilog airhdl.com/blog/2022/04/1…

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airhdl @airhdl

4 years ago

New Feature: Markdown Generator airhdl.com/blog/2021/11/0… #FPGA #VHDL #SystemVerilog #AXI4

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airhdl @airhdl

4 years ago

Journey into Open Source VHDL Verification Frameworks (part 2) by @colombini_caen looks at how to use the #UVVM library to interact with an @airhdl generated register bank link.medium.com/oTmgj7sTQkb

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airhdl @airhdl

5 years ago

airhdl now supports field enumerated values airhdl.com/blog/2020/04/2… #FPGA

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airhdl @airhdl

6 years ago

Upon popular request, airhdl now supports packing user-facing ports into #SystemVerilog structs.

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airhdl @airhdl

6 years ago

Shiny and New: the Register Calculator airhdl.com/blog/2019/09/0… #FPGA #VHDL #SystemVerilog

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Guy Eschemann @geschema

6 years ago

Here's a preview of the upcoming register calculator in airhdl youtu.be/cUvjp3_n5A0

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airhdl @airhdl

7 years ago

Did you know? @airhdl supports self-clearing register fields. Those will automatically clear one cycle after they have been written -- super convenient for controlling resets in your user logic. #FPGA #RegisterGenerator #VHDL #Verilog #SystemVerilog