asicdv @asicdv

If you are looking for a comprehensive online series on #RISC-V design, look no further. Here is a nice course by Trivandrum College of Engineering youtube.com/channel/UCUXXs… Presentation dedicated to PULP: youtu.be/Dn-PFmZ7kMo

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asicdv @asicdv

5 years ago

🧑🏽‍🚒

Eric LaForest @elaforest

6 years ago

🧑🏽‍🚒

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asicdv @asicdv

5 years ago

Apparently it’s recommend not to use local variables inside SVA but rather go for a mix of assertions and procedural. Thinker.

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asicdv @asicdv

5 years ago

While searching landed on this page once. Glad I found it again. It’s a succinct cheat sheet for SVA.

Peter Monsson @SVAssertions

5 years ago

While searching landed on this page once. Glad I found it again. It’s a succinct cheat sheet for SVA.

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asicdv @asicdv

5 years ago

Don’t overthink when you write assertions. Try to keep simple.

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asicdv @asicdv

5 years ago

When you use clock range operator there might be situation where you end up with False Positive cases. Solution is to use local variables in those cases.

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asicdv @asicdv

5 years ago

Suppose for every clock cycle you need to check if a signal is toggling. @(posedge clk) toggle ##1 !toggle; But there is caveat here Above SVA is contradicting toogle true value to previous false value. This would do, @(posedge clk) ##1 $changed(toggle);

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asicdv @asicdv

5 years ago

Remainder: Whenever you write always keep KISS principle in mind. Keep it simple and stupid.

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ShaktiProcessors @ShaktiProcessor

5 years ago

Shakti processor based Grand Challenge.. participate now !

Ravi Shankar Prasad @rsprasad

5 years ago

Shakti processor based Grand Challenge.. participate now !

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Download Video

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Dennis Brophy @dennisbrophy

5 years ago

What's next to boost verification productivity? Read what may come your way shortly. lnkd.in/gvKYf5M

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asicdv @asicdv

5 years ago

I’m looking forward to attend this webinar. Basically simulink itself has efficient HDL code generation that can be used for fixed point logic so then why do you need catapult HLS. #Simulink #RTL #ASIC

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asicdv @asicdv

5 years ago

Finally got chance to attend @dvclub thanks to the online event this time. So much information regarding various aspects of verification: methodologies, approaches, language etc. Hopefully online event stay beyond lockdown period. @ParadigmWorks @mentor_graphics