Dougall @dougallj

he/they | mastodon: https://t.co/d5YdiePIr8 / @[email protected] du.gl Joined February 2007

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Chipwise @chipwise_tech

7 days ago

Here it is! Die shot of Apple's A19 SoC🔥🔬 chipwise.tech/our-portfolio/…

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Dougall @dougallj

3 weeks ago

My view. x.com/dougallj/statu…

Dougall @dougallj

3 years ago

My view. x.com/dougallj/statu… https://t.co/UB64ph2H6E

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hikari 🌟 (fell out of the sky) @hikari_no_yume

a year ago

very sad that cohost is going. maybe its unique genre of posting, the css crime, will go with it. well, i'm glad that there's this worthy goodbye to it cohost.org/rebane2001/pos…

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After 27 years of providing in-depth coverage of the amazing world of PC and mobile hardware, AnandTech is saying farewell. We want to thank everyone from the AnandTech community for their support and passion for what we’ve done over the years anandtech.com/show/21542/end…

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Rui Ueyama @rui314

a year ago

CRC checksum is not a cryptographic hash function. It is easy to add a few bytes of garbage at the end of a file so that the CRC of the entire file becomes a desired value. But did you need to do that in the linker? Yes. github.com/rui314/mold/bl…

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Andreas Schilling 🇺🇦 @aschilling

a year ago

Analysis of the M4 by @techinsightsinc „key design choice in the Apple M4 is the use of TSMC's high-performance standard cell library for CPU1“ …“UHD libraries for GPU and CPU2“ aka TSMC FinFlex CPU1: P-Cores CPU2: E-Cores techinsights.com/blog/introduci…

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Jon Masters 🏴‍☠️ @jonmasters

a year ago

Starting to think this @Arm thing might have legs

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INIYSA @lafaiel

a year ago

Intel is now essentially following Apple's design philosophy, with an integrated memory architecture, a large front-end, a large L1 cache, removal of SMT, 4+4 cores

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Dougall @dougallj

a year ago

"Vulkan 1.3 on the M1 in 1 month", by Alyssa Rosenzweig rosenzweig.io/blog/vk13-on-t…

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Alexander Yee @Mysticial

a year ago

With Lisa's keynote over, I will casually drop this to confirm that y-cruncher v0.8.5 will get #Zen5 optimizations with it's big and fat #AVX512. Release date still ETA - pending final silicon. x.com/Mysticial/stat… ST and BBP will be where the light shines the brightest.

Alexander Yee @Mysticial

a year ago

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Pete Cawley @corsix

a year ago

@dyaroshev @geofflangdale @HaroldAptroot @FUZxxl FWIW, I've also given it a decent write-up at corsix.org/content/abusin…. Only notable change is putting maskz on the shuffle rather than on the permutexvar, as uops.info suggests maskz costs a few cycles, so might as well put it on the cheaper of the two instructions.

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Nat Brown @[email protected] @natbro

a year ago

Fantastical deep information about optimizing for Apple Silicon can now be found here: developer.apple.com/download/apple…

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clamchowder @lamchester

2 years ago

Example of why power draw is a poor proxy for how well a program is utilizing your hardware (i7-7700K CPU in this case). In one case, execution port use is heavy and IPC is high, so the CPU's pipeline is running at high utilization. However power draw is low. Second case...