luke k.c. leighton @lkcl

Ethical Libre Software Developer and Advocate Eco-conscious Libre Hardware Designer lkcl@fizzy:~/src/libresoc/soc$ ps auxww | grep "vi " | wc 1510 lkcl.net The World. (Planet Earth) Joined March 2009

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David Harold @dcharold

2 years ago

My newsletter has one subscriber. Me. Help me change that over on LinkedIn. Week 1 includes #AI, #biotech, #cleantech, #spacetech, and #semiconductors. Plus a touch of #SciFi. linkedin.com/newsletters/th…

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luke k.c. leighton @lkcl

2 years ago

indico.cern.ch/event/1231545/ OSSYM2023 at @CERN 5th International Symposium on Open Search deadline is 31st May

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it took me a while to notice that ARM has special instructions for linked-list-pointer-chasing alastairreid.github.io/papers/sve-iee… however i am delighted to confirm that SVP64 Vector instructions for linked-list-chasing works. @OpenPOWERorg

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Christopher Allen @ChristopherA

2 years ago

This is important work! Help ensure it continues by becoming a @BlockchainComns sponsor. [13/13] github.com/sponsors/Block…

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Christopher Allen @ChristopherA

2 years ago

This week’s Silicon Salon 4 explored the challenges and offered some insights into solutions at the intersection of cryptography and semiconductor manufacturing. Explore the presentations by Andrew Poelstra, Red Semiconductor, and @cramiumlabs now! [1/13] siliconsalon.info/salon4/

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Christopher Allen @ChristopherA

2 years ago

Luke Leighton @lkcl & David Calderwood will overview the missing RISC ISA instructions related to biginteger operations [3/5].

Christopher Allen @ChristopherA

2 years ago

Luke Leighton @lkcl & David Calderwood will overview the missing RISC ISA instructions related to biginteger operations [3/5].

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luke k.c. leighton @lkcl

2 years ago

doing the write-up for OPF ISA WG External RFC ls016 - Integer Twin-Butterfly DCT/FFT "mul-add-sub-shift-imm" libre-soc.org/openpower/sv/t… the number of instructions it replaces is *eight*. and it's in-place. no temp regs. massive savings. @IBMResearch @OpenPOWERorg @GanesanBlue

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luke k.c. leighton @lkcl

2 years ago

with many thanks to @NgiSearch and @FundingBox we will be optimising the SVP64 Draft ISA (proposed to the @OpenPOWERorg ISA WG last week) for Search. VectorCamp will be porting VectorScan to SVP64, Vantosh optimising libc6 string/memory routines linkedin.com/feed/update/ur…

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blu (🇺🇦 in NATO) @blu51899890

3 years ago

> Meanwhile, the processor's stream performance with eight channels of DDR4-3200 memory crosses the 50GB mark. Wow! /he exclaimed, while reading this article on an tablet-grade arm SoC doing 65GB/s of RAM BW tomshardware.com/news/loongson-…