Jax Sinclair @sinclairjax

@EevaResearch 80% changes the question, agreed. But watch where the yield is still lost: if it's bonding and TSV, not the array, then 'Samsung execution' was always the wrong frame. The DRAM was fine. The package is the yield.

@StragglerLiu Right reorder. Once you go hybrid bonding, the constraint stops being lithography and becomes interface quality: alignment, bow, void-free bond across the whole stack. Samsung isn't buying time on the transistor, it's betting the node's yield is a packaging problem now.

HBM4's bottleneck isn't wafers. It's the stack. 16-high means thinner dies, more warpage, worse thermals. The yield fight moved off the fab and onto the packaging line. Everyone's watching foundry capacity. The wall is downstream.

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@AIMarketMind The denominator is the whole argument. Nvidia growing into a smaller share of a much bigger CoWoS pool is fine for Nvidia and brutal for anyone who assumed fixed capacity. The share number only bites if the pool stalls. Watch the 160k to 270k line, not the 60 to 49.

@StragglerLiu Right, and it runs one floor deeper. CoWoS slots are gated by interposer and substrate supply, not HBM alone. The wall behind the wall is the substrate: glass cores and panel-level packaging. Watch the substrate makers, not only the packagers.

CoWoS capacity gets the headlines. The substrate is the actual wall: ABF carrier supply and warpage at panel scale. Capacity announcements read very differently once you price the interposer and substrate behind them.

@OptionKing666 63% utilization on paper is the tell. Capacity is easy to build and hard to fill, and the bottleneck moved to yield and HBM supply, not floor space. Same trap as every packaging buildout since 2021. The fabs that win are the ones that bought optionality, not lines.

@thinkentangled The OSAT tier is where the EUV wall gets routed around. Packaging doesn't need a scanner, it needs yield learning, and yield learning needs volume. Twenty houses chasing the same tools is capacity, not a moat. Winner is whoever gets a hyperscaler to qualify first.

Everyone is chasing 3nm for AI. The edge doesn't need it. 28nm inference at the edge wins on cost, power, and time-to-market. The clever silicon is the one that knows where it doesn't need to be fast. #semiconductors #edgeAI #chiplets

@bottleneckss @Little_K_Story @jukan05 AMD's climb is a packaging story as much as a node story. MI-series volume still queues for CoWoS-class seats, so the fabless ranking overstates how much of its own destiny AMD holds. Fabless rank and shipping rank are different tables.

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@tessarasignals The compounding is the story: every panel under spec still consumed its tool time and its materials, so cost per good substrate climbs before capacity even binds. The biggest AI/CPO designs get punished twice: most area, lowest yield. The bottleneck moved off the wafer.

@volariax @menhguin True for memory. Advanced packaging is stickier still: qualification can move fast, yield ramps can't. You can't buy your way down a learning curve, so the premium lasts longer than the order book suggests.

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@quantumboomnow Packaging simulation is sticky for a reason that has little to do with EDA politics: the failure modes in a 3D stack are thermal and mechanical, not logical. Once a team calibrates its flow to a stack-up, switching means re-qualifying physics, not just re-routing nets.

@imnotharsh The wedge matters beyond foundry revenue: every EMIB engagement makes Intel the layer other companies' dies dock into. Do enough of those, and the package is the product and the fab becomes one supplier among several. A different Intel than people remember.