ultraembedded @ultraembedded

CPU designs, digital HW IP, emulation and embedded system projects github.com/ultraembedded UK Joined April 2020

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ultraembedded @ultraembedded

4 years ago

I couldn’t resist - just ordered a zynq 7020 and another ArtyA7 😀

Digilent @DigilentInc

4 years ago

I couldn’t resist - just ordered a zynq 7020 and another ArtyA7 😀

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Bruno Levy @BrunoLevy01

4 years ago

How to create your own FPU at home, new #femtorv32 tutorial on how 'petitbateau' floats ! github.com/BrunoLevy/lear…

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Great news! The Ph.D. thesis of our Ariane guru Florian @be4web is now online! You can find it in the Research Collection of ETH Zurich under the title "Energy-Efficient High-Performance Computing" research-collection.ethz.ch/bitstream/hand…

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nickmqb @nickmqb

4 years ago

The FPGA Minecraft clone is now open source! github.com/nickmqb/fpga_c…

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Bruno Levy @BrunoLevy01

4 years ago

#femtorv32-petitbateau Major refactoring, now FPU is a separate Verilog module (to ease reuse in other projects)

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Jan Gray @jangray

4 years ago

#FPGA Here Palacharla, Jouppi, Smith explore this for a conventional (instruction granularity) ISA, wherein the i-fetch stream is steered into n FIFOs each with this X,Y,Z issue dependence. Then you only have to determine which FIFO heads are ready... jes.ece.wisc.edu/papers/isca97.… 2/

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Enjoy Digital @enjoy_digital

4 years ago

The minimal LiteX port of MicroPython is now available at github.com/litex-hub/micr… and can run on almost all boards supported by LiteX-Boards, want to try it? Here running on a @GOWIN_SEMI GW1NR9 with VexRiscv RV32IM + LiteDRAM (8MB embedded SDRAM) + boot from SPI SDCard.

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ultraembedded @ultraembedded

4 years ago

Just adding an RTL project to opencores.org (not sure why really). How has that website languished in such a dire state for nearly 22 years?! Whoever owns it can't be making any money from it, so why not turn it over to the open-source community so it can fixed?

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ultraembedded @ultraembedded

4 years ago

First attempt at using Yosys+nextpnr-xilinx today (for Artix7). Same design, but not really a fair bitstream build time comparison as Yosys was running on an Apple M1 (i.e. ARM64) vs Vivado on an i5-8500B. Xilinx doesn't do a Vivado ARM64 version, so 😀

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ultraembedded @ultraembedded

4 years ago

Released another RISC-V core: github.com/ultraembedded/… It doesn't win any performance awards, but it is small, multi-cycle, RV32I+M, configurable, simple, and hopefully well verified. Not as small as @BrunoLevy01 #femtorv32, but 12x fewer LUTs than my dual-issue biRISC-V core!

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ultraembedded @ultraembedded

4 years ago

OpenFPGALoader (by @GwenhaelG) loads bitstreams onto my ArtyA7 in half the time of that bloated whale Vivado... github.com/trabucayre/ope…

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LambdaConcept @LambdaConcept

4 years ago

#Tensorflow lite model accelerated on the FPGA using dedicated CNN cores around our #lambdasoc and our #minerva RISC-V CPU. The demo uses our ECPIX5 board. blog.lambdaconcept.com/post/2021-06/f…

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Sylvain Lefebvre @sylefeb

4 years ago

Silice #verilator framework update! All graphical #Silice demos (Doom-chip, Terrain, ...) simulate with on-screen display. Don't own an #FPGA yet? Simply `make verilator` and get started! 1/5 github.com/sylefeb/Silice… (special thanks to @WillFlux, see next)